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Integrated Circuit Systems, Inc.
ICS9248-131
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: ALI - Aladdin V - mobile style chipsets Output Features: 3 - CPUs @ 2.5/3.3V, up to 100MHz. 3 - AGPCLK @ 3.3V 13 - SDRAM @ 3.3V 6 - PCI @ 3.3V 1 - 48MHz, @ 3.3V fixed. 1 - REF @ 3.3V, 14.318MHz. Features: Support power management: CPU, PCI, AGP stop and Power down Mode from I2C programming. Spread spectrum for EMI control. Uses external 14.318MHz crystal FS pins for frequency select Key Specifications: CPU CPU: <250ps AGP PCI: <550ps CPU(early)-PCI: 1-4ns, Center 2-6ns
Pin Configuration
VDDF *REF0/CPU2.5_3.3# GND X1 X2 VDDPCI *PCICLK_F/FS1 *PCICLK0/FS2 GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDA BUFFERIN GND *CPU_STOP#/SDRAM11 *PCI_STOP#/SDRAM10 VDDSDR *AGP_STOP#/SDRAM9 *PD#/SDRAM8 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDAGP AGP0 AGP1 GND CPUCLK0 CPUCLK1 VDDL CPUCLK2 SDRAM12 GND SDRAM0 SDRAM1 VDDSDR SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDSDR SDRAM6 SDRAM7 GND 48MHz/FS0* AGP_F/MODE*
48-Pin SSOP
Block Diagram
PLL2 48MHz
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Functionality
FS2 FS1 1 1 0 0 1 1 0 0 FS0 1 0 1 0 1 0 1 0 CPU, SDRA M (MHz) 100 95.25 83.3 97 91.5 96.22 66.67 60 PCI (MHz) 33.33 31.75 33.30 32.33 30.50 32.07 33.33 30.00 AGP (MHz) 66.67 63.50 66.60 64.66 61.00 64.15 66.67 60.00 1 1 1 1 0 0 0 0
X1 X2
XTAL OSC PLL1 Spread Spectrum
REF
CPU DIVDER
Stop
3
CPUCLK (2:0)
CPU2.5_3.3# SDATA SCLK FS (2:0) PD# PCI_STOP# CPU_STOP# SDRAM_STOP# AGP-STOP# MODE BUFFERIN Control Logic
PCI DIVDER
Stop
5
PCICLK (4:0) PCICLK_F
AGP DIVDER
Stop
2
AGP (1:0) AGP_F
Note: REF & IOAPIC = 14.318MHz
Config. Reg.
Power Groups
Analog
13
Digital VDDPCI VDDSDR VDDAGP
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
SDRAM (12:0)
VDDF VDDA
9248-131 Rev B 7/17/00
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-131
ICS9248-131
Pin Descriptions
PIN NUMBER 1, 6, 14, 19, 30, 36, 48 2 C P U 2 . 5 _ 3 . 3 # 1,2 3,9,16,22,27, 33,39,45 4 5 GND X1 X2 PCICLK_F 7 FS11, 2 8 13, 12, 11, 10 15 17 PCICLK0 FS21, 2 PCICLK(4:1) BUFFERIN CPU_STOP#1 SDRAM 11 18 40, 28, 29, 31, 32, 34, 35, 37, 38 20 PCI_STOP# SDRAM 10 SDRAM (12, 7:0) AGP_STOP# SDRAM9 21 23 24 25 PD# SDRAM8 SDATA SCLK AGP_F MODE1, 2 48MHz 26 41, 43, 44 42 46, 47 FS01, 2 CPUCLK(2:0) VDDL AGP (1:0)
1
P I N NA M E VDD REF0
TYPE PWR OUT IN PWR IN OUT OUT IN OUT IN OUT IN IN OUT IN OUT OUT IN OUT IN OUT I/O IN OUT IN OUT IN OUT PWR OUT Power supply, nominal 3.3V 14.318 Mhz reference clock.
DESCRIPTION
Indicates whether VDDL is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V C P U 1. L a t c h e d i n p u t 2 Ground Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew (CPU early) This is not affected by PCI_STOP# Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Frequency select pin. Latched Input PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Input pin for SDRAM buffers. Halts CPUCLK clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output Halts PCICLK clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock output SDRAM clock outputs. This asynchronous input halts AGP clocks at logic "0" level when input low (in Mobile Mode, MODE=0) Does not affect AGP0 SDRAM clock output This asyncheronous Power Down input Stops the VCO, crystal & internal clocks when active, Low. (In Mobile Mode, MODE=0) SDRAM clock output Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant Advanced Graphic Port output, Not affected by AGP_STOP# Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 48MHz output clock for USB timing. Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. CPU clock outputs, powered by VDDL. Low if CPU_STOP#=Low Supply for CPU, either 2.5V or 3.3V nominal Advanced Graphic Port outputs
Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
2
ICS9248-131
General Description
The ICS9248-131 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-131 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. The SDRAM12 output may be used as a feed back into an off chip PLL.
Mode Pin - Power Management Input Control
MODE, Pin 25 (Latched Input) 0 1 Pin 17 CPU_STOP# (INPUT) SDRAM 11 (OUTPUT) Pin 18 PCI_STOP# (INPUT) SDRAM 10 (OUTPUT) Pin 20 AGP_STOP# (INPUT) SDRAM 9 (OUTPUT) Pin 21 PD# (INPUT) SDRAM 8 (OUTPUT)
Power Management Functionality
AGP_STOP# CPU_STOP# PCI_STOP# 1 1 1 0 0 1 1 1 1 1 0 1 AGP, CPUCLK Outputs Stopped Low Running Running Running PCICLK (4:0) Running Running Stopped Low Running PCICLK_F, REF, 48MHz and SDRAM Running Running Running Running Crystal OSC Running Running Running Running VCO Running Running Running Running AGP (1:0) Running Running Running Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5 Input level (Latched Data) 1 0 Buffer Selected for operation at: 2.5V VDD 3.3V VDD
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ICS9248-131
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Description Bit7 Bit2 Spread Spectrum Method 0,0 +/- 0.25% Center Spread Spectrum Modulation Bit 7,2 0,1 +/- 0.15% Center Spread Spectrum Modulation 1,0 0 to -0.5 Down Spread Spectrum Modulation 1,1 +/- 0.375% Center Spread Spectrum Modulation Bit6 Bit5 Bit4 CPU Clock PCI AGP 111 100 33.33 66.67 110 95.25 31.75 63.50 101 83.3 33.30 66.60 Bit 6:4 100 97 32.33 64.66 011 91.5 30.50 61.00 010 96.22 32.07 64.15 001 66.67 33.33 66.67 000 60 30.00 60.00 0 - Frequency is selected by hardware select, Latched inputs Bit 3 1 - Frequency is selected by Bit 6:4 (above) 0 - Normal Bit 1 1 - Spread Spectrum Enabled 0 - Running Bit 0 1 - Tristate all outputs Bit PWD
0,0
Note1 001
0 0 0
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 001, and if bit 3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle. Note: PWD = Power-Up Default
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 41 43 44 PWD 1 X X 1 1 1 1 1 Description (Reserved) FS2# FS1# SDRAM12 (Act/Inact) (Reserved) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 7 13 12 11 10 8 PWD X 1 X 1 1 1 1 1 Description CPU2.5_3.3# PCICLK_F (Act/Inact) FS0# PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0(Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. I2C is a trademark of Philips Corporation
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
4
ICS9248-131
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 29 31 32 34 35 37 38 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 (Act/Inact) SDRAM6 (Act/Inact) SDRAM5 (Act/Inact) SDRAM4 (Act/Inact) SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact)
Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 25 17 18 20 21 PWD 1 1 1 1 1 1 1 1 Description AGP_F (Active/Inactive) (Reserved) (Reserved) (Reserved) SDRAM11 (Act/Inact) (Desktop Mode Only) SDRAM10 (Act/Inact) (Desktop Mode Only) SDRAM9 (Act/Inact) SDRAM8 (Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 47 46 2 PWD 1 1 1 1 1 X 1 1 Description (Reserved) (Reserved) (Reserved) AGP0 (Act/Inact) (Reserved) MODE AGP1 (Act/Inact) REF0 (Act/Inact)
Byte 6: Optional Register for Possible Furture Requirements
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Byte 6 is reserved by Integrated Circuit Systems for futue applications.
5
ICS9248-131
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD =VDDL= 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD VIN = 0 V; Inputs with no pull-up resistors Input Low Current IIL1 VIN = 0 V; Inputs with pull-up resistors Input Low Current IIL2 CL = 0 pF; Select @ 66 MHz IDD3.3OP Operating Supply Current CL = 0 pF; Select @ 100 MHz VDD = 3.3 V Input frequency Fi CIN Logic Inputs CINX X1 & X2 pins Ttrans To 1st crossing of target Freq Transition Time1 1 Ts From 1st corssing to 1% target Freq Settling Time Clk Stabilization1 TSTAB From VDD = 3.3 V to 1% target Freq. TCPU-PCI Vt=1.5 V; f=66 / 100 Mhz; CPU leads Skew1 TAGP-PCI Vt = 1.5V; AGP Leads ( Vdd+/-5% 25C) 1 Guaranteed by design, not 100% tested in production. Input Capacitance1 MIN 2 VSS-0.3 -5 -200 MAX UNITS VDD+0.3 V 0.8 V 5 uA uA uA 105 160 mA 140 160 mA 14.318 16 MHz 5 45 2 2 2 4 550 pF pF ms ms ms ns ps TYP
12 27
1
2 300
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5%, VDDL=2.5V +/- 5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN CL = 0 pF; Select @ 66.8 MHz IDDL2.5 Operating Supply Current CL = 0 pF; Select @ 100 MHz TCPU-PCI1 Vt=1.5 V; f=66 / 100 Mhz; CPU leads 1 Skew1 TAGP-PCI1 Vt = 1.5V; AGP Leads ( Vdd+/-5% 25C) TYP 8 15 2 300 MAX 15 20 4 550 UNITS mA ns ps
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ICS9248-131
Electrical Characteristics - CPU
TA = 0 - 70C; VDD=VDDL=3.3V +/- 5%; CL = 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
MIN 13.5 13.5 2.5
TYP 30 32
MAX UNITS 45 45 0.4 -23 V V mA mA ns ns % ps ps
RDSP2B
1 1
VO=VDD*(0.5) VO=VDD*(0.5) IOH = -28 mA IOL = 27 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
1
RDSN2B VOH2A VOL2A IOH2A IOL2A tr2A1 tf2A1 dt2A1 tsk2A1
33 1.1 1.6 50 52 130 130 2 2 55 250 250
Duty Cycle Skew window1
1 1
Jitter, Cycle-to-cycle1 tjcyc-cyc2A VT = 1.5 V Guaranteed by design, not 100% tested in production. Edge displacement of a period relative to a 10-clock-cycle rolling average period.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD=3.3V, VDDL=2.5V, both +/- 5%; CL = 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
TYP 30 32
MAX UNITS 45 45 0.4 -16 V V mA mA ns ns % ps ps
RDSP2B
1 1
VO=VDD*(0.5) VO=VDD*(0.5) IOH = -8 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
1
13.5 13.5 2
RDSN2B VOH2B VOL2B IOH2B IOL2B tr2B
1 1 1 1
19 1 1.3 45 50 130 130 1.8 1.8 55 250 250
tf2B
Duty Cycle Skew window1
1 1
dt2B
tsk2B
Jitter, Cycle-to-cycle1 tjcyc-cyc2A VT = 1.5 V Guaranteed by design, not 100% tested in production. Edge displacement of a period relative to a 10-clock-cycle rolling average period.
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ICS9248-131
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3V +/-5%; CL = 30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
MIN 12 12 2.4
TYP 24 23
MAX UNITS 55 55 0.4 -40 V V mA mA ns ns % ps ps
RDSP2B
1 1
VO=VDD*(0.5) VO=VDD*(0.5) IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
RDSN2B VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1
41 1.7 1.5 45 50 305 100 2.3 2.0 55 500 500
Duty Cycle Skew window1 Jitter, Cyc-to-Cyc
1
tsk1 tjcyc-cyc1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD=VDDL=3.3V +/-5%; CL = 30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current SD (0:1,3:12) Rise Time SD(0:1,3:12) Fall Time
1 1 1
MIN 12 12 2.4
TYP 24.19 23.08
MAX UNITS 55 55 0.4 -40 V V mA mA ns ns % ns ns % ns ps
RDSP2B
1 1
VO=VDD*(0.5) VO=VDD*(0.5) IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
RDSN2B VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tr1 tf1 dt1
41 1.4 1.5 50 54 1.8 1.9 50 54 4 350 2 2 58 2.4 2.4 58 6 500
SD(0:1,3:12) Duty Cycle SD 2 Rise Time1 SD 2 Fall Time
1 1
SD 2 Duty Cycle Propagation Delay Skew window1
1
Tprop tsk1
Guaranteed by design, not 100% tested in production.
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ICS9248-131
Electrical Characteristics - AGP
TA = 0 - 70C; VDD=VDDL=3.3V +/-5%; CL = 30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
MIN 12 12 2.4
TYP 24.19 23.08
MAX UNITS 55 55 0.4 -40 V V mA mA ns ns % ps ps ps
RDSP2B
1 1
VO=VDD*(0.5) VO=VDD*(0.5) IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
1
RDSN2B VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1
41 1.3 1.4 45 48 100 120 500 2 2 55 250 250 850
Duty Cycle Skew window1 Jitter Cyc-Cyc, AGP(1:2) Jitter Cyc-Cyc, AGP_F
1
tjcyc-cyc1 tjcyc-cyc
VT = 1.5 V VT = 1.5 V
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz
TA = 0 - 70C; VDD = VDDL = 3.3V +/-5%; CL = 10 - 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1
MIN 20 20 2.4
TYP 47 44
MAX UNITS 60 60 0.4 -22 V V mA mA ns ns % ns
RDSP2B
1 1
VO=VDD*(0.5) VO=VDD*(0.5) IOH = -16 Ma IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
RDSN2B VOH5 VOL5 IOH5 IOL5 tr51 tf5
1 1 1
16 2.3 2.3 45 50 0.7 4.0 4.0 55 1
Duty Cycle REF Jitter, Cyl-to-Cyl
1
dt5
tj1s5
Guaranteed by design, not 100% tested in production.
9
ICS9248-131
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS9248-131
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 11
ICS9248-131
AGP_STOP# Timing Diagram
AGP_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the AGP clocks. for low power operation. AGP_STOP# is synchronized by the ICS9248-131. The AGPCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. AGPCLK on latency is less than AGPCLK and AGPCLK off latency is less than 4 AGPCLKs. This function is available only with MODE pin latched low.
Notes: 1. All timing is referenced to the internal CPUCLK. 2. AGP_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9248-131. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
5. Only applies if MODE pin latched 0 at power up.
12
ICS9248-131
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-131. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL CPUCLK PCICLK CPU_STOP# PCI_STOP# (High)
CPUCLK, AGP SDRAM
Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-131. 3. All other clocks continue to run undisturbed. (including SDRAM outputs).
13
ICS9248-131
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-131. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-131 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248 device. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
14
ICS9248-131
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK AGP PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-131 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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ICS9248-131
SY MBOL
In Millimeters COMMON DIMENSIONS MIN MA X 2.413 0.203 0.203 2.794 0.406 0.343
In Inches COMMON DIMENSIONS MIN MA X .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N V A RIA TIONS N 28 34 48 56 64
0.127 0.254 SEE V A RIA TIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE V A RIA TIONS .395 .291 .015 .420 .299 .025
0.635 BA SIC 0.508 1.016 SEE V A RIA TIONS 0 8
0.025 BA SIC .020 .040 SEE V A RIA TIONS 0 8
D mm. MIN 9.398 11.303 15.748 18.288 20.828 MA X 9.652 11.557 16.002 18.542 21.082 MIN .370 .445 .620 .720 .820
D (inc h) MA X .380 .455 .630 .730 .830
6/1/00 R E VB
J E DEC MO- 118 DOC# 10- 0034
Ordering Information
ICS9248yF-131-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
16
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

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